Semiconductor integrated circuit device

ABSTRACT

Disclosed herein is a peripheral LSI containing a number of microprocessor peripheral IPs. Even when the peripheral IPs are integrated, this peripheral LSI can prevent the package price from rising, the power consumption from increasing, and the software designers from being perplexed. A switch of the programmable peripheral LSI is provided for electrically disabling peripheral IPs. As a result, the peripheral IPs are disabled while they are not used.

FIELD OF THE INVENTION

[0001] The present invention relates to an embedded microprocessor andits peripheral LSI that are incorporated in cellular phones, cameras,and other system devices. More particularly, the present inventionrelates to a hardware-programmable peripheral LSI carrying peripheralIPs for the interfaces of various peripheral devices, a one-chipmicroprocessor incorporating said LSI and CPU core, and a device forevaluating and verifying embedded systems with said LSI andmicroprocessor mounted on board.

BACKGROUND OF THE INVENTION

[0002] A wide variety of interface protocols are used for data exchangeamong computers, peripheral devices such as hard disk drives andscanners, and cellular phone, digital camera, and video systems. Aone-chip microprocessor, which is integrated with a CPU core andperipheral IPs conforming to various interface protocols, is developedto support a wide variety of interfaces. The term “peripheral IPs” usedin the present application refer to circuit modules that provide aninterface for connecting the CPU core to external devices.

[0003] Within this type of microprocessor, all of its peripheral IPs arenot used at all times. Since some peripheral IPs are not used, it isnecessary to exercise control so as to enable/disable the peripheralIPs.

[0004] One control method is to provide each peripheral IP with acontrol register so that the CPU core enters a command for each controlregister via a peripheral bus to specify whether the associatedperipheral IP should be enabled or disabled (first conventionaltechnology).

[0005] The method stated in JP-A No. 289051/1999 is to use aprogrammable circuit, which is typically represented by an FPGA. Aprogrammable circuit is integrated with an MPU and various interfacecircuits. This programmable circuit is used after LSI manufacture todetermine the wiring connections between the MPU and various interfacecircuits. As a result, various interface sets can be supported by asingle LSI (second conventional technology).

[0006] As the number of interfaces to be supported by the CPU core, thenumber of peripheral IPs increases, causing the following problems:

[0007] When the first conventional technology is used, the increase inthe number of peripheral IPs may increase the number of output pins,thereby raising the package price. Further, even when some peripheral IPcircuits are disabled by a command, they still run in a sleep mode,allowing unnecessary power consumption to continue. The term “sleepmode” refers to a mode of operation in which the command transmissionfrom the CPU or a device outside the LSI is monitored. If there are manyunnecessary peripheral IPs, the software designer may also be perplexed.

[0008] When the second conventional technology is used, the MPU andinterface circuits are directly connected by the programmable circuit.Therefore, the resulting configuration differs from the microprocessor'scommon configuration, which is established via a bus. That is why theconfiguration based on the second conventional technology isinapplicable to general-purpose processors. Further, the secondconventional technology has not disclosed a configuration that wouldreduce the amount of unnecessary power consumption.

[0009] In a volume production of an LSI, it is possible to develop anLSI that carries only necessary peripheral IPs. In limited production ofdiversified products, however, the development cost of such an LSI wouldturn out to be excessive. If a single kind of LSI can be commonly usedfor limited production of diversified products, it is possible to reducethe development cost and shorten the development period.

SUMMARY OF THE INVENTION

[0010] The first object of the present invention is to offer asemiconductor integrated circuit device suitable for a general-purposeLSI that can be adopted for the limited production of diversifiedproducts.

[0011] The second object of the present invention is to offer a methodof efficiently developing a system or an LSI for use with a system,using an evaluation chip carrying peripheral IPs.

[0012] To solve the above problems, a peripheral IP selection switch isfurnished as a hardware-programmable means of disabling the peripheralbus connections for unnecessary peripheral IPs in compliance with a userrequest. The switch is necessary for excluding the influence ofperipheral IP operations upon the other circuits and essential fordisabling unnecessary IPs.

[0013] The programmable peripheral LSI to be connected to the CPU coreor the microprocessor integrated with the programmable peripheral LSIand CPU core is to be offered, with the switch mounted, as avolume-production LSI. In addition, a board carrying the CPU core,programmable peripheral LSI, and program storage non-volatilesemiconductor memory is to be offered as an evaluation board.

[0014] Furthermore, the power consumption can be reduced by shutting offthe power supply to the peripheral IPs to be disabled.

[0015] Other and further objects, features and advantages of theinvention will appear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the attached drawings:

[0017]FIG. 1 shows the structure of the programmable peripheral LSI fora first exemplary embodiment of the present invention;

[0018]FIG. 2 shows the structure of the switch;

[0019]FIG. 3 is a block diagram of a chip set that uses the programmableperipheral LSI of the present invention;

[0020]FIG. 4 is a block diagram of a microprocessor that is obtained byintegrating the programmable peripheral LSI and CPU core into a singlechip;

[0021]FIG. 5 is a system/LSI design flowchart of a second exemplaryembodiment of the present invention;

[0022]FIG. 6 is a block diagram of an evaluation board that uses theprogrammable peripheral LSI of the present invention; and

[0023]FIG. 7 shows how the evaluation board and system evaluation boardof the present invention are used for evaluation/verification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiments of the present invention are detailed below withreference to drawings.

First Exemplary Embodiment

[0025]FIG. 1 is a block diagram of a programmable peripheral LSI thatincorporates peripheral IPs for supporting various interface protocolsand a switch for selecting such peripheral IPs.

[0026] An LSI chip 2 is molded by an LSI package 1. The LSI package 1has pads 3 for external connection. The pads 3 are connected toterminals 7 on the LSI chip 2. The LSI chip 2 has peripheral IPs 5,which are connected to a peripheral bus 4 via a switch 6.

[0027] For example, a peripheral IP 5-1 is an IrDA interface circuit forIrDA wireless communication. Peripheral IPs 5-2 to 5-5 are interfacecircuits for IEEE1394, USB, SCI, and SIO, respectively, all of whichprovide wired communication. Although FIG. 1 shows one peripheral IP foreach kind of peripheral IP, two or more peripheral IPs of one kind ofperipheral IP can be incorporated.

[0028] The switch 6 has a program input terminal 7-7. The input terminal7-7 is connected to a pad 3-5. The program for specifying theeffectivity of peripheral IPs is to be entered via the pad 3-5.

[0029] The peripheral bus 4 is connected to a bus terminal 7-6. The busterminal 7-6 is connected to a pad 3-4. Data is exchanged with aperipheral bus (not shown in the figure) external to the LSI via the pad3-4. Being connected to a pad 3-6, a power supply terminal 7-8 receivesa power supply potential from the outside of the LSI via the pad 3-6.

[0030] In the example shown in FIG. 1, peripheral IPs 5-2 to 5-4 areenabled whereas peripheral IPs 5-1 and 5-5 are disabled. In thisexample, the peripheral IPs to be disabled are not connected to any pad.The use of this configuration makes it possible to use a package havinga decreased number of pads and reduce the cost of the package.

[0031]FIG. 2 is used to explain about the method of enabling anddisabling the peripheral IPs of the present invention. The switch 6 hasswitching elements 23 and 24. The switching element 23 is provided forthe line connecting a RAM 21, peripheral IP 5, and peripheral bus 4. Theswitching element 24 is provided for the line connecting the powersupply terminal 7-8 and peripheral IP 5.

[0032] For example, the switching element 23, which is a component ofthe switch 6, can be implemented by an MOS transistor (the presentinvention uses the term “MOS transistor” for representing an insulatedgate type field effect transistor) having a source-drain path in theconnection path between a peripheral IP and peripheral bus 4. Switchingelements composing a switch 23-1 for peripheral IP 5-1 are controlled bya common, first control signal. Switching elements composing a switch23-2 for peripheral IP 5-2 are controlled by a common, second controlsignal.

[0033] Similarly, the switching elements composing a switch 24 can alsobe implemented by an MOS transistor. Switch 24-1 for peripheral IP 5-1is controlled by said first control signal. Switch 24-2 for peripheralIP 5-2 is controlled by the second control signal.

[0034] When a switching element is turned ON by a control signal, thefunction of data transfer between a peripheral IP and peripheral bus isenabled with a power supply potential supplied. Therefore, theperipheral IP is enabled. On the other hand, when a switching element isturned OFF by a control signal, the function of data transfer between aperipheral IP and peripheral bus is disabled with no power supplypotential supplied. Therefore, the peripheral IP is disabled. The RAM 21stores these control signals in such a manner that value of a storedcontrol signal for turning ON a switching element is 1, and that thevalue of a stored control signal for turning OFF a switching element is0.

[0035]FIG. 3 shows a typical chip set that carries a programmableperipheral LSI of the present invention. LSIs are mounted on a board 31and interconnected by a peripheral bus 4 and memory bus 37. An externalsignal or power supply potential is entered into these LSIs via adaptors38 and signal lines.

[0036] A programmable peripheral LSI 33 correlates to the LSI shown inFIG. 1. It is connected to a CPU core LSI 34 via the on-board peripheralbus 4. As indicated in the figure, the programmable peripheral LSI 33 ofthe present invention employs a bus and therefore complies with thegeneral chip set configuration requirements.

[0037] Further, a non-volatile semiconductor memory 36 is mounted on theboard. This memory stores control data that is to be written into theRAM 21 (see FIG. 2).

[0038] When the board is configured in the above-mentioned manner, adesired CPU core can be used at the time of system configuration toselect a desired peripheral IP from those incorporated in the peripheralLSI 33 for use. Consequently, the flexibility of system design can beincreased. Although FIG. 3 indicates that the chips are mounted on theboard, they can be mounted in a single package to form a multi-chippackage (MCP).

[0039] For ease of understanding, FIG. 3 discloses major data signallines only. It goes without saying that the other data signal lines,control signal lines, power supply lines, and other lines also exist.The same holds true for the other drawings as well.

[0040]FIG. 4 shows a modified version of the example shown in FIG. 1.The example shown in FIG. 4 is a microprocessor 42, which is formulatedby integrating a peripheral LSI chip 2 and CPU core 41 into a singlechip. The advantage to this embodiment is that it can increase thedegree of integration by integrating a CPU and peripheral IPs into asingle chip.

Second Exemplary Embodiment

[0041] In the second exemplary embodiment, the LSI shown in FIG. 1 isused for system verification.

[0042]FIG. 5 shows a system/LSI design flowchart. The term “system”refers to mobile information devices such as a cellular phone and PDA.Various LSIs, liquid-crystal panel, and other components are mounted onsuch a board. The left-hand half of FIG. 5 shows the flowchart for asystem maker. The right-hand half of FIG. 5 shows the flowchart for asemiconductor maker.

[0043] The system maker performs system design (step 501). This step isperformed to design the entire system and determine the portions to beimplemented by software and the portions to be implemented by hardware.The portions to be implemented by hardware are assembled into aso-called ASIC (Application Specific Integration Circuit). At this time,a semiconductor maker offers (step 510) in compliance with a systemmaker's request an evaluation board carrying a CPU core 34 andperipheral LSI 33, which are described later with reference to FIG. 6.The system maker uses the evaluation board to conduct pre-designestimation (step 502) and decide on the CPU core to be offered as anASIC.

[0044] In pre-design estimation 502, the evaluation board is used tocheck whether the specifications are met by the performance of softwareexecuted by the CPU core 34 and the capability of data transfer to aperipheral device via the CPU core and peripheral LSI 33. In this sense,the pre-design estimation exerts a great influence upon the decision onthe CPU core and the semiconductor maker who supplies the CPU core.

[0045] When the CPU core is decided on, the system maker complies withthe system design criteria to perform software design (step 503) and LSIdesign (step 504), which provides ASIC design, and verifies such designs(step 505). The semiconductor maker offers design support and designenvironment to the system maker (step 520).

[0046] Step 505 contains step 506 for software verification, step 507for ASIC verification, and step 508 for system level verification withan evaluation board supplied by the semiconductor maker. System levelverification 508 is performed simultaneously with software verification506 and LSI verification 507 when the latter two verification steps areperformed to a certain extent. The reason is that a higher degree ofverification efficiency can be achieved than by conducting system levelverification after completion of software/LSI verification.

[0047] When verification is completed in step 505, the system makerdelivers design data to the semiconductor maker. LSI layout data andlogic gate level data are both acceptable as the design data. The choicebetween these two types of data is made in accordance with the systemmaker's LSI design capability and agreement with the semiconductormaker. The semiconductor maker creates a real chip in compliance withthe design data supplied by the system maker (step 511). The systemmaker performs system verification 509 with the supplied real chip. Uponcompletion of system verification, the system maker instructs thesemiconductor maker to start a volume production of the chip.

[0048] The semiconductor maker does not have to complete all steps510-511 by itself.. The semiconductor maker may cowork with itsaffiliated companies to perform these tasks.

[0049]FIG. 6 shows the structure of the evaluation board. The evaluationboard 61 carries the peripheral LSI 33, PLD 63 (FPGA or otherprogrammable circuit), CPU core 34, and non-volatile semiconductormemory 36. All of these components are sealed packages of semiconductorchips. The peripheral LSI 33 is structured as shown in FIG. 1 and FIG.2. The CPU core 34 is connected to the peripheral LSI 33 via theperipheral bus 4. Further, the CPU core 34, PLD 63, and systemevaluation board interface 66 are interconnected via a memory bus 37.The user's logic supplied by the system maker is programmed in the PLD63. The non-volatile semiconductor memory 36 stores the control data(stored in the RAM 21 shown in FIG. 2) for selecting a peripheral IP ofthe peripheral LSI 33 and the user's logic to be programmed in the PLD63, and is electrically reprogrammable.

[0050] When the evaluation board is used, a desired peripheral IP of theperipheral LSI is selected, and the user's logic is programmed in thePLD 61 to conduct evaluation and verification. Eventually, an ASIC iscreated by integrating into a single chip the CPU core 34, theuser-selected peripheral IP of peripheral LSI 33, and the user's logicprogrammed in the PLD 63.

[0051]FIG. 7 shows how the evaluation board is used. The evaluationboard 61 is mounted on the user's system evaluation board 71. A powersupply 72 supplies power to the evaluation board 61 and systemevaluation board 71. Further, system level evaluation and verificationare conducted by operating software 74 with the evaluation board 61connected to a PC 73 on which an emulator/debugger runs. In someconventional evaluation/verification equipment containing a number ofperipheral IPs, each peripheral IP was implemented by an LSI. In such aninstance, however, the overall evaluation/verification equipment washoused within a casing and could not be mounted on the system evaluationboard 71. Even when the programmable peripheral LSI 33 contains a numberof unnecessary peripheral IPs, the present invention makes it possibleto offer a compact board without having to develop dedicatedevaluation/verification equipment.

[0052] On the basis of a peripheral LSI containing a number ofperipheral IPs, it is possible to offer at a minimum development cost aperipheral LSI that would be equal in the number of pins and powerconsumption to an LSI incorporating only peripheral IPs necessary forthe user.

[0053] Further, when said LSI is-used as ASIC evaluation/verificationequipment, it is possible to cut the development cost for suchequipment.

[0054] The invention may be embodied in other specific forms withoutdeparting from the spirit or essential characteristics thereof. Thepresent embodiment is therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims rather than by the foregoingdescription and all changes which come within the meaning and range ofequivalency of the claims are therefore intended to be embraced therein.

What is claimed is:
 1. A semiconductor integrated circuit device whichcomprises: a first circuit module complying with a first interfaceprotocol, a second circuit module complying with a second interfaceprotocol, a peripheral bus, a first switching element for connectingsaid first circuit module to said peripheral bus, and a second switchingelement for connecting said second circuit module to said peripheralbus, wherein said first switching element turns ON to enable said firstcircuit module and said second switching element turns OFF to disablesaid second circuit module.
 2. The semiconductor integrated circuitdevice according to claim 1, further comprising: a power supplypotential point for supplying a power supply potential, a thirdswitching element for connecting said first circuit module to said powersupply potential point, and a fourth switching element for connectingsaid second circuit module to said power supply potential point, whereinsaid third switching element turns ON to enable said first circuitmodule and said fourth switching element turns OFF to disable saidsecond circuit module.
 3. The semiconductor integrated circuit deviceaccording to claim 2, wherein a first control signal controls the statusof said first switching element and said third switching element, and asecond control signal controls the status of said second switchingelement and fourth switching element.
 4. The semiconductor integratedcircuit device according to claim 3, further comprising a memory forstoring said first control signal value and said second control signalvalue, which are, that is, hardware programmed data.
 5. Thesemiconductor integrated circuit device according to claim 4, whereinsaid memory stores hardware program data that is entered from theoutside of said semiconductor integrated circuit device.
 6. Asemiconductor integrated circuit device according to claim 1, furthercomprising a CPU core.
 7. A method of designing a system, whichcomprises the steps of: determining a first section of said system to beimplemented by software and a second section of said system to beimplemented by hardware, designing software for said first section,designing an integrated circuit for said second section, verifying saiddesigned software, verifying said designed integrated circuit, andverifying said system with an evaluation board, wherein said evaluationboard contains a CPU core package, a peripheral LSI package comprisingcircuit modules related to interface protocols, and a programmablecircuit package; and said programmable circuit package is used toprogram a user's logic for said designed integrated circuit and saidperipheral LSI package enables either of said circuit modules for aspecified interface protocol.
 8. The method of designing a systemaccording to claim 7, wherein the step of verifying said system isperformed simultaneously with the steps of verifying said software andsaid integrated circuit.
 9. An evaluation board which comprises: a CPUcore package, a peripheral LSI package comprising circuit modulesrelated to interface protocols, a programmable circuit package, a memorybus for connecting said CPU core package to said programmable circuitpackage, and a peripheral bus for connecting said CPU core package tosaid peripheral LSI package, wherein circuit modules of said peripheralLSI package are selectively enabled.
 10. The evaluation board accordingto claim 9, wherein said programmable circuit package is used to programa user's logic.
 11. The evaluation board according to claim 9, furthercomprising a non-volatile semiconductor memory for storing a controlsignal, wherein said control signal enables/disables the circuit modulesof said peripheral LSI package.